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order this document by mc68360d mc68360 product brief mc68360 quad integrated communication controller (quicc ) introduction the mc68360 quad integrated communication controller (quicc ) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. it particularly excels in communications activities. the quicc (pronounced ?uick? can be described as a next-generation mc68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. the term "quad" comes from the fact that there are four serial communications controllers (sccs) on the device; however, there are actually seven serial channels: four sccs, two serial management controllers (smcs), and one serial peripheral interface (spi). quicc key features the following list summarizes the key mc68360 quicc features: cpu32+ processor (4.5 mips at 25 mhz) 32-bit version of the cpu32 core (fully compatible with the cpu32) background debug mode byte-misaligned addressing up to 32-bit data bus (dynamic bus sizing for 8 and 16 bits) up to 32 address lines (at least 28 always available) complete static design (0?5-mhz operation) slave mode to disable cpu32+ (allows use with external processors) multiple quiccs can share one system bus (one master) mc68040 companion mode allows quicc to be an mc68040 companion f r e e s c a l e s e m i c o n d u c t o r , i f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
memory (sram), electrically programmable read-only memory (eprom), flash eprom, etc. four cas lines, four we lines, one oe line boot chip select available at reset (options for 8-, 16-, or 32-bit memory) special features for mc68040 including burst mode support four general-purpose timers superset of mc68302 timers four 16-bit timers or two 32-bit timers gate mode can enable/disable counting two independent dmas (idmas) single address mode for fastest transfers buffer chaining and auto buffer modes automatically performs efficient packing 32-bit internal and external transfers system integration module (sim60) bus monitor double bus fault monitor spurious interrupt monitor software watchdog periodic interrupt timer low power stop mode clock synthesizer breakpoint logic provides on-chip hardware breakpoints external masters may use on-chip features such as chip selects on-chip bus arbitration with no overhead for internal masters ieee 1149.1 test access port interrupts seven external irq lines 12 port pins with interrupt capability 16 internal interrupt sources programmable priority between sccs programmable highest priority request communications processor module (cpm) risc controller many new commands (e.g., graceful stop transmit, close rxbd) 224 buffer descriptors supports continuous mode transmission and reception on all serial channels f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
four sccs ethernet/ieee 802.3 optional on scc1 (full 10-mbps support) (available only on the mc68en360) hdlc/sdlc (all four channels supported at 2 mbps) hdlc bus (implements an hdlc-based local area network (lan)) appletalk signaling system #7 universal asynchronous receiver transmitter (uart) synchronous uart binary synchronous communication (bisync) totally transparent (bit streams) totally transparent (frame based with optional cyclic redundancy check (crc)) profibus (ram microcode option) asynchronous hdlc (ram microcode option) to support ppp (point to point protocol) ddcmp (ram microcode option) v.14 (ram microcode option) x.21 (ram microcode option) two smcs uart transparent general circuit interface (gci) controller can be connected to the time-division multiplexed (tdm) channels one spi superset of the mc68302 scp supports master and slave modes supports multimaster operation on the same bus time-slot assigner supports two tdm channels each tdm channel can be t1, cept, pcm highway, isdn basic rate, isdn primary rate, user defined 1- or 8-bit resolution allows independent transmit and receive routing, frame syncs, clocking allows dynamic changes can be internally connected to six serial channels (four sccs and two smcs) parallel interface port f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc architecture overview the quicc is 32-bit controller that is an extension of other members of the freescale m68300 family. like other members of the m68300 family, the quicc incorporates the intermodule bus (imb). (the mc68302 is an exception, having an m68000 bus on chip.) the imb provides a common interface for all modules of the m68300 family, which allows freescale to develop new devices more quickly by using the library of existing modules. although the imb definition always included an option for an on-chip 32-bit bus, the quicc is the first device to implement this option. the quicc is comprised of three modules: the cpu32+ core, the sim60, and the cpm. each module utilizes the 32-bit imb. the mc68360 quicc block diagram is shown in figure 1. external bus interface system protection sim 60 cpu32+ core imb (32 bit) risc controller system i/f 2.5-kbyte dual-port ram dram controller and chip selects cpm periodic timer clock generation other features breakpoint logic jtag communications processor four general- purpose timers interrupt controller other features timer slot assigner seven serial channels two idmas fourteen serial dmas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
fetch two word-length instructions in one bus cycle, filling the internal instruction queue more quickly. the cpu32+ core can also read and write 32-bits of data in one bus cycle. although the cpu32+ instruction timings are improved, its instruction set is identical to that of the cpu32. it will also execute the entire m68000 instruction set. it contains the same background debug mode (bdm) features as the cpu32. no new compilers, assemblers, or other software support tools need be implemented for the cpu32+; standard cpu32 tools can be used. the cpu32+ delivers approximately 4.5 mips at 25 mhz, based on the standard (accepted) assumption that a 10-mhz m68000 delivers 1 vax mips. if an application requires more performance, the cpu32+ can be disabled, allowing the rest of the quicc to operate as an intelligent peripheral to a faster processor. the quicc provides a special mode called mc68040 companion mode to allow it to conveniently interface to members of the m68040 family. this two-chip solution provides a 22-mips performance at 25 mhz. the cpu32+ also offers automatic byte alignment features that are not offered on the cpu32. these features allow 16 or 32-bit data to be read or written at an odd address. the cpu32+ automatically performs the number of bus cycles required. system integration module (sim60) the sim60 integrates general-purpose features that would be useful in almost any 32-bit processor system. the term ?im60?is derived from the quicc part number, mc68360. the sim60 is an enhanced version of the sim40 that exists on the mc68340 and mc68330 devices. first, new features, such as a dram controller and breakpoint logic, have been added. second, the sim40 was modified to support a 32-bit imb as well as a 32-bit external system bus. third, new configurations, such as slave mode and internal accesses by an external master, are supported. although the quicc is always a 32-bit device internally, it may be configured to operate with a 16-bit data bus. regardless of the choice of the system bus size, dynamic bus sizing is supported. bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode. communications processor module (cpm) the cpm contains features that allow the quicc to excel in communications and control applications. these features may be divided into three sub-groups: communications processor (cp) two idma controllers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
the four general-purpose timers on the quicc are functionally similar to the two general-purpose timers found on the mc68302. however, they offer some minor enhancements, such as the internal cascading of two timers to form a 32-bit timer. the quicc also contains a periodic interval timer in the sim60, bringing the total to five on-chip timers. upgrading designs from the mc68302 since the quicc is a next-generation mc68302, many designers currently using the mc68302 may wish to use the quicc in a follow-on design. the following paragraphs briefly discuss this endeavor in terms of architectural approach, hardware issues, and software issues. architectural approach the quicc is the logical extension of the mc68302, but the overall architecture and philosophy of the mc68302 design remains intact in the quicc. the quicc keeps the best features of the mc68302, while making the changes required to provide for the increased flexibility, integration, and performance requested by customers. because the cpm is probably the most difficult module to learn, anyone who has used the mc68302 can easily become familiar with the quicc since the cpm architectural approach remains intact. the most significant architectural change made on the quicc was the translation of the design into the standard m68300 family imb architecture, resulting in a faster cpu and different system integration features. although the features of the sim60 do not exactly correspond to those of the mc68302 sim, they are very similar. the quicc sim60 combines the best mc68302 sim features with the best mc68340 sim features for improved performance. because of the similarity of the quicc sim60 and cpu to other members of the m68300 family, such as the mc68332 and the mc68340, previous users of these devices will be comfortable with these same features on the quicc. hardware compatibility issues the following list summarizes the hardware differences between the mc68302 and the quicc: pinout?he pinout is not the same. the quicc has 240 pins; the mc68302 has 132 pins. package?oth devices offer pga and pqfp packages. however, the quicc pqfp package has a 20-mil pitch; whereas, the mc68302 pqfp package has a 25-mil pitch. system bus?he system bus signals now look like those of the mc68030 as opposed to those of the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the mc68302. software compatibility issues the following list summarizes the major software differences between the mc68302 and the quicc: since the cpu32+ is a superset of the m68000 instruction set, all previously written code will run. however, if such code is accessing the mc68302 peripherals, it will require some modification. the quicc contains an 8-kbyte block of memory as opposed to a 4-kbyte block on the mc68302. the register addresses within that memory map are different. the code used to initialize the system integration features of the mc68302 has to be modified to write the corresponding features on the quicc sim60. code written for the mc68340 may be adapted in large part. as much as possible, quicc cpm features were made identical to those of the mc68302 cp. the most important benefit is that the code flow (if not the code itself) will port easily from the mc68302 to the quicc. the nuances learned from the mc68302 will still be useful in the quicc. although the registers used to initialize the quicc cpm are new (for example, the scm on the mc68302 is replaced with the gsmr and psmr on the quicc), most registers retain their original purpose such as the scc event, scc mask, scc status, and command registers. the parameter ram of the sccs is very similar, and most parameter ram register names and usage are retained. more importantly, the basic structure of a buffer descriptor (bd) on the quicc is identical to that of the mc68302, except for a few new bit functions that were added. (in a few cases, a bit in a bd status word had to be shifted.) when porting code from the mc68302 cp to the quicc cpm, the software writer may find that the quicc has new options to simplify what used to be a more code-intensive process. for specific examples, see the init tx and rx parameters, graceful stop transmit, and close bd commands. quicc glueless system design a fundamental design goal of the quicc was ease of interface to other system components. an example of this goal is a minimal quicc design using eprom and dram, shown in figure 2. this system interfaces gluelessly to an eprom and a dram simm module. it also offers parity support for the dram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc mc68360 ce (enable) oe (output enable) we (write) data address 8-bit boot eprom (flash or regular) cs0 oe we0 data address ras cas3?as0 w (write) data address parity 16- or 32-bit dram simm (optional parity) ras1 cas3?as0 r/w prty3?rty0 figure 2. minimum quicc system configuration figure 3 shows a larger system configuration. this system offers one eprom, one flash eprom, and supports two dram simms. depending on the capacitance on the system bus, external buffers may be required. from a logic standpoint, however, a glueless system is maintained. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc mc68360 ce (enable) oe (output enable) we (write) data address 8-bit boot eprom (flash or regular) cs0 oe we0 data address ras cas3?as0 w (write) data address parity 16- or 32-bit two dram simms (optional parity) ras1 cas3?as0 r/w ras buffer e (enable) g (output enable) w (write) data address 8-, 16-, or 32-bit sram cs7 we3?e0 ras2 prty3?rty0 figure 3. larger quicc system configuration quicc serial configurations the quicc offers an extremely flexible set of communications capabilities. although a full understanding of f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc quicc quicc scc1 ethernet scc1 scc1 mc68160 eest mc68160 eest mc68160 eest figure 4. ethernet lan capability figure 5 shows how up to six of the serial channels can connect to a tdm interface. the quicc provides a built-in time-slot assigner for access to the tdm time slots. other channels can work with their own set of pins, allowing possibilities like an ethernet to t1 bridge, etc. quicc time division multiplexed bus t1, cept, idl, gci, isdn, primary rate, user-defined time slot assigner scc scc scc scc smc smc any combination of sccs and smcs may be connected to the tdm. note: independent receive and transmit clocking, routing, and syncs are supported. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc time slot assigner scc scc scc scc smc smc any combination of sccs and smcs may be connected to any tdm. tdm bus 1 tdm bus 2 note: two tdm buses may be simultaneously supported with the time slot assigner. figure 6. dual tdm bus implementation quicc serial configuration examples figure 7 shows a general-purpose application that includes ethernet, appletalk, an hdlc connection to a t1 line, an hdlc connection to frame relay, a uart debug monitor port, a totally transparent data stream port, and an spi connection to a serial eeprom. quicc scc1 scc2 scc3 scc4 smc2 spi ethernet rs-422 apple talk t1 line transceiver x.25 (hdlc) rs-232 frame relay (hdlc) rs-232 uart serial eeprom system bus time slot assigner freescale sia transceiver f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
quicc master quicc slave cpu32+ quicc system bus scc scc scc scc smc smc spi scc scc scc scc smc smc spi cpu32+ figure 8. master-slave quicc implementation the quicc has special features in slave mode to support the m68040 family. when the quicc is used in this way, it is said to be in mc68040 companion mode. figure 9 shows how a quicc in slave mode can interface to a mc68ec040. (the mc68ec040 is a low-cost version of the mc68040 with identical integer performance, but without the memory management unit (mmu) and the floating-point unit (fpu).) the dram controller on the quicc will control the accesses of the mc68ec040 (including the burst modes). this configuration does require external address mutiplexers, but the quicc controls the multiplexers. the quicc supports the mc68ec040 in other ways, such as interrupt handling and system protection features. when it is in slave mode, the quicc can also be interfaced to any mc68030-type bus master instead of the mc68ec040. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68ec040 quicc slave cpu32+ system bus scc scc scc scc smc smc spi memory controller control address muxs sram mc68ec040 support functions eprom dram figure 9. mc68040 companion mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
the following table identifies the packages and operating frequencies available for the mc68360. mc68360 package/frequency availability package type frequency (mhz) temperature order number quad flat pack (em suffix) quad flat pack (em suffix) quad flat pack with ethernet quad flat pack with ethernet 0?5 0?5 0?5 0?5 0 c to 70 c ?0 c to +85 c 0 c to 70 c ?0 c to +85 c mc68360em25 tbd MC68EN360EM25 tbd pin grid array (rc suffix) pin grid array (rc suffix) pin grid array with ethernet pin grid array with ethernet 0?5 0?5 0?5 0?5 0 c to 70 c ?0 c to +85 c 0 c to 70 c ?0 c to +85 c mc68360rc25 tbd mc68en360rc25 tbd the documents listed in the following table contain detailed information on the mc68360. these documents may be obtained from the literature distribution centers at the addresses listed at the bottom of this page. documentation document title order number contents mc68360 user's manual mc68360um/ad detailed information for design m68000 family programmer's reference manual m68000pm/ad m68000 family instruction set the 68k source br729/d independent vendor listing supporting software and development tools f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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